NS新的模数转换器12位 ADC12C170具有1.1GHz带宽和业界最高的SFDR,很适合WiMAX的应用.它的工作电压为+/-1.8和+/-3.3V, 170 MSPS时的功耗仅为715mW,而降功耗时的功耗为5mW.

       采用内部取样和保持电路以及差分输入,使输入幅度能达到基准电压的两倍,广泛应用在无线基站接收机,多载波多模式接收机,雷达系统,通信基础设备以及功率放大器的线性化.本文提供了ADC12C170的方框图,以及详细的应用电路图和所用材料清单(BOM).

      National Semiconductor’s New 12-Bit ADCs for WiMAX Provide the Industry’s Highest SFDR of 84.1 dB at 250 MHz Input Frequency

      The ADC12C170 is a high-performance CMOS analog-to digital converter capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample- and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full power bandwidth of 1.1 GHz. The ADC12C170 operates from dual +3.3V and +1.8V power supplies and consumes 715 mW of power at 170 MSPS.

      The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 5 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

      The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12C170 can be operated with an external reference.

      Clock mode (differential versus single-ended) and output data format (offset binary versus 2s complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

      The ADC12C170 is pin compatible with the ADC14155, ADC11C125 and ADC11C170.
      
      It is available in a 48-lead LLP package and operates over the industrial temperature range of 40°C to +85°C.

      主要特性:
     ■ 1.1 GHz Full Power Bandwidth
     ■ Internal sample-and-hold circuit
     ■ Low power consumption
     ■ Internal precision 1.0V reference
     ■ Single-ended or Differential clock modes
     ■ Clock Duty Cycle Stabilizer
     ■ Dual +3.3V and +1.8V supply operation
     ■ Power-down and Sleep modes
     ■ Offset binary or 2s complement output data format
     ■ Pin-compatible: ADC14155, ADC11C125, ADC11C170
     ■ 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

     主要指标:
     ■ Resolution 12 Bits
     ■ Conversion Rate 170 MSPS
     ■ SNR (fIN = 70 MHz) 67.2 dBFS (typ)
     ■ SFDR (fIN = 70 MHz) 85.4 dBFS (typ)
     ■ ENOB (fIN = 70 MHz) 10.8 bits (typ)
     ■ Full Power Bandwidth 1.1 GHz (typ)
     ■ Power Consumption 715 mW (typ)

     应用范围:
     ■ High IF Sampling Receivers
     ■ Wireless Base Station Receivers
     ■ Power Amplifier Linearization
     ■ Multi-carrier, Multi-mode Receivers
     ■ Test and Measurement Equipment
     ■ Communications Instrumentation
     ■ Radar Systems
     图1.ADC12C170方框图:

图2.采用变压器驱动的应用电路图

图3. ADC12C170LFEB模拟输入网络(FIN < 150 MHz)

图4.ADC12C170评估板外形图.

图5.信号电路图:

                                                     图6.电源分布图:

      下表为所用材料清单(BOM):

      ADC12C170数据表:

      http://cache.national.com/ds/DC/ADC12C170.pdf

      或

      http:///appinfo/adc/files/ADC12C170MAN.pdf