si5324主要特性:

generates any frequency from 2 khz to 945 mhz and select frequencies to 1.4 ghz from an input frequency of 2 khz to 710 mhz

ultra-low jitter clock outputs as low as 290 fs rms (12 khz–20 mhz), 320 fs rms (50 khz–80 mhz)

integrated loop filter with selectable loop bandwidth (4– 525 hz)

meets itu-t g.8251 and telcordia gr253-
图1.si5324方框图

图2.si5324典型应用电路图(i2c控制模式)

图3.si5324典型应用电路图(spi控制模式)