领先的半导体设备供应商Aviza Technology日前推出一款面向3D IC通孔硅技术（TSV）应用的200mm/300mm集成式系统。

Versalis fxP基于Aviza经生产验证的单晶圆平台，拥有6个工艺模块，其中深度硅刻蚀、PVD及CVD已经通过多项量产验证，包括：晶圆级封装、MEMS及功率半导体等。“一站式”的解决方案通过降低安装成本减小占地面积，给客户研发工作带来显著成本效益。

“Aviza在刻蚀、PVD及CVD领域拥有专业的技术，创新型的Versalis fxP系统为3D IC通孔硅技术研发机构提供了独特的集成工艺解决方案。”Aviza公司PVD/CVD/刻蚀业务副总裁兼总经理Kevin Crofton表示，“Aviza三大领域的专业技术将使客户深深受益，以经济有效的方式开发TSV工艺并转向量产。”

使用TSV技术的3D IC应用广泛，包括NAND闪存、图像传感器、DSP、DRAM、SRAM、FPGA、Memory、处理器、无线LAN放大器、手机通讯及军事等应用。市场研究机构Yole Developpment公司预计到2012年3D IC晶圆年复合增长率将达到60%。

Yole Developpment市场分析师Jerome Baron表示：“随着各项新技术的开发，3D IC市场增长显著。在众多技术中，TSV优势明显。而为TSV提供工艺集成式服务的系统对工艺开发非常重要。”

Aviza Technology Introduces Versalis fxP
First of its Kind System Offers Integrated Processing Solution on a Single
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SCOTTS VALLEY, Calif.--(BUSINESS WIRE)-- Aviza Technology, Inc.
(NASDAQ:AVZA), a supplier of advanced semiconductor capital equipment and
process technologies for the global semiconductor industry and related
markets, today announced the introduction of the Versalis fxP, a 200/300 mm
cluster system targeted for 3D-IC manufacturing using through silicon via
(TSV) technology. Aviza is at the forefront of developing this unique
integrated process solution for research and development (R&D) that
encompasses multiple steps, including Etch, PVD and CVD, in order to
deliver functional 3D-IC packages and accelerate time-to-market for such
products.
The Versalis fxP is based on Aviza’s production-proven single-wafer
platform, which can incorporate up to six process modules. Its individual
modules such as deep silicon etch, PVD and CVD have all been proven in
high-volume manufacturing for various applications including wafer level
packaging, MEMS and power semiconductors. The Versalis fxP platform
combines all of the critical processes needed to create a via ready for
plating. This “one-stop shop” solution enables customers to invest less
capital for R&D, minimizing installation costs and optimizing use of their
fab area.
“By leveraging Aviza’s process expertise in the areas of etch, PVD and CVD,
the company has introduced an innovative system, the Versalis fxP, which
offers a unique integrated processing solution to the R&D community
focusing on 3D-ICs using TSV technology,” said Kevin Crofton, Vice
President and General Manager, PVD/CVD/Etch Business Unit of Aviza
Technology, Inc. “Customers will benefit from Aviza’s process expertise in
these three process areas in order to meet our customers’ manufacturing
requirements for next-generation 3D architectures. On one platform,
customers can develop their TSV processes in a cost-effective and efficient
manner with the ability to seamlessly migrate them to the production
environment.”
TSV Approach
Three key elements are driving the design of advanced consumer products,
increased functionality, reduced size and lower cost. These are the very
same drivers that are pushing the adoption of 3D-ICs and the associated
required packaging technologies. The two most common technologies for 3D-IC
packaging are wire bonding and TSV to establish the electrical connectivity
between the components of the stacked die.
An increasingly important factor in favor of TSV is that it can consume up
to 30 percent less Silicon than the wire-bonded equivalent, because wire
bonding can only connect around the periphery of the device. Recently, the
raw cost of Silicon has risen over 10x fueled by solar cell demand,
significantly changing the cost comparison picture between TSV and wire
bonding. Further, this requirement for additional Silicon to satisfy
wire-bonders means that less die can be manufactured on the source wafer,
putting additional pressure on profit margins. In addition, TSV is gaining
wider adoption by 3D-IC manufacturers, as this approach has demonstrated
the ability to keep the interconnect distance very short and removes any
real limitation on the number of die that can be stacked in this manner. As
a result, TSVs can enable smaller form factor devices and has demonstrated
improved device speed and functionality.
3D-ICs using TSV technology have numerous applications, including NAND
Flash Memory, Image Sensors, Sensors and DSP, DRAM, SRAM, FPGA and Memory,
Processors, Amplifiers for Wireless LAN, Communication for Mobile Phones
and Military applications. Leading market research firm Yole Développment
forecasts the compounded annual growth rate (CAGR) for 3D-IC wafers to be
above 60 percent by 2012.
“The 3D-IC arena is clearly a growth market with increased activity on
numerous fronts,” said Jér?me Baron, Market Analyst at Yole Développment.
“TSV processes have shown significant device and performance benefits over
other methods. An integrated process approach for TSV will play a critical
role in streamlining the development process.”
Unique Integrated Processing Capabilities
For R&D and pilot production, the ideal system solution would be a single
toolset capable of four critical, individual process steps in TSV
formation: TSV etch, CVD liner & liner etch and PVD. The unique advantage
of such an approach enables dramatically shortened TSV development time.
With all three process technologies (etch, PVD and CVD) on board, the
Versalis fxP offers much smaller footprint, compared to three individual
systems, and a single install minimizing cost and disruption to the
cleanroom, thus reducing the overall development and processing time to
deliver the first wafer out. In addition, this type of system allows R&D
users to link separate processes without breaking vacuum to discover
potential performance benefits, and then apply those findings to optimally
configure production systems—which would not be possible on traditionally
configured single-process systems.
For full volume production capability, the individual process modules would
be installed onto additional handlers, each one dedicated to each of the
separate processes—a feature offered by the Versalis fxP system. This
approach can only be realized if the process modules all shared common
mechanical interface and control systems. This leads to minimal process
re-qualification, an additional advantage for adopting an integrated
hardware and process approach for TSV-based 3D packaging.